1. Field of the Invention
The present invention relates generally to a semiconductor package stack arranged to be mounted on a printed circuit board (PCB), and, more particularly, to a semiconductor package stack which provides reduced electrical noise, comprising a conductive film formed on an exposed bottom surface of the chip of each semiconductor package of the stack, each conductive film being grounded to ground lines of the PCB.
2. Description of the Prior Art
Recently, there has been a trend towards making modules and surface mounting packages compact and thin in order to provide highly dense mounting of semiconductor packages. In compliance with this trend, compact and thin packages such as TSOP (Thin Small Outline Package) and UTSOP (Ultra Thin Small Outline Package) have been developed, and these packages are used mainly for main memory devices of computers.
The integration density of IC (Integrated Circuit) devices can be increased by forming finely the elements which constitute the IC and the metal wiring which connects these elements. However, this method is difficult to put into practical use, due to limitations present in fabrication.
To avoid these problems, methods for increasing mounting density by mounting a highly dense packaged module, or by stacking high density chips, in a three-dimensional arrangement has been proposed. A highly dense mounting of chips on a substrate such as a printed circuit board can be accomplished by mounting a plurality of surface-mounting chips or TAB (Tape Automated Bonding) packages on the substrate.
However, as very large scale integrated (LSI) circuits tend to get more complex, there is a need to switch more output driver circuits simultaneously, at a faster rate, in order to increase the performance thereof. This increase in the switching speed results in an increase in the amount of electrical noise which is associated therewith. Therefore, various attempts for reducing or minimizing the noise associated with the increase in the switching rate have been made.
For example, U.S. Pat. No. 4,945,399 to Brown discloses a semiconductor chip package wherein additional capacitors such as decoupling capacitors are coupled between the associated voltage pins.
Another example is a semiconductor device stack disclosed in U.S. Pat. No. 5,198,888 to Toshio Sugano et al. U.S. Pat. No. 5,198,888 teaches semiconductor device stack as shown in FIG. 1A.
With reference to FIG. 1A, the semiconductor package stack (100) has a structure wherein four semiconductor packages (10) are stacked on a substrate, for example, PCB (80) by using connectors (frames) (40). The frame (40) is surface-mounted on a land pattern (82) formed on the PCB (80) so that a chip (21) of the package (10) is located above a capacitor (60) formed on a capacitor land pattern (82).
To describe in more detail, for the lowest (first) package (10) of the stack, an extended outer lead (22) is electrically connected to a circuit pattern (43) formed on the upper surface of the frame (40) of the lowest package with solder (91). The circuit pattern (43) is connected to a circuit pattern (44) formed on the lower surface of the frame (40) of the second lowest package of the stack by solder (91). For the second lowest package (10), an extended outer lead (22) is electrically connected to a circuit pattern (43) formed on the frame (40) of the second package by solder (91), and the respective circuit pattern (44) is electrically connected to the circuit pattern (43) formed on the lower surface of the frame (40) of the third stacked package with solder (91). Consequently, there is formed a space between the bottom surface of chip of the second stacked package (10) and the upper surface of the resin (28) of the first stacked package (10).
The third and fourth packages are consecutively stacked above the second stacked package by following the same fabrication process.
Thus fabricated, a semiconductor package stack (100) is mounted on the PCB (80) in such a way that the circuit patterns (44) formed on the bottom surface of the frame (40) of the first stacked package are connected to land patterns (82) of the PCB by solder (91).
The packages (10) each has a structure in which bonding pads (not shown) are formed on the upper surface of the chip (21), leads (22) are formed on an insulating film (26) of a tape carrier, an internal part of each lead (22) is electrically connected to the corresponding bonding pad by a respective bump (24), and the chips (21), bumps (24) and leads (22) are encapsulated in a body of resin (28) so that the bottom surface of the chip and extended outer parts of the leads (22) are exposed.
Each frame (40) is formed with circuit patterns (43) and (44) on the upper and lower surfaces thereof, and formed with vertical through holes (42), which are indicated in FIG. 1(A) by broken lines. Conductive thin layers are formed on the bonding surfaces of the respective through holes, and electrically connect the circuit patterns (43) and (44) of each frame (40) to one another.
The PCB (80) is formed so as to have land patterns (82) on its upper surface, and a capacitor (60) is formed on the capacitor land pattern (82) which faces the bottom surface of the first stacked package (10).
The land patterns (82) of the PCB (80), the circuit patterns (43), (44) formed on the upper and lower surfaces of the frames (40), the leads (22) of the package (10), bonding pads of the chips (21) and ground lines (not shown) of the PCB (80) are electrically interconnected.
For the above-described package stack (100), the capacitor (60) is designed to serve as a noise filter when mounting the package stack (100) on the land patterns (82) of the PCB (80).
FIG. 1(B) is a cross-sectional view for showing the working effect of the package stack depicted in FIG. 1(A), wherein a MOS (Metal Oxide Semiconductor) element is formed with a PN diode between a silicon substrate and an active area thereof.
With reference now to FIG. 1(B), electric noise can be reduced to some extent by grounding the n+ embedded layer to the p+ embedded layer by a capacitor.
The conventional package having bumps has an exposed bottom surface of silicon substrate, while the top surface has internal terminals of the chip, which are connected to the external terminals. The diode formed between the substrate and the active area to which a Vss voltage pin is not connected is designed to have a reverse bias and, consequently, is turned off during an operation. However, in the case of an alternating current operation, because a lower electric potential is formed at the active area and the diode has a forward bias, the diode is turned on, resulting in an unstable operation of elements. This is the same for the N-type substrate.
The discrete capacitors formed depart away from the semiconductor chip are electrically connected to the chip by a plurality of wiring lines or large power buses. The wiring lines are a representative example of high inductance paths. As the current of wiring lines increases, the scale of voltage drop increases, which results in undesired power distribution noise. Consequently, the electrical noise can be reduced by forming the capacitors as near the chip as possible, to reduce, effective inductance of the current path.
Nevertheless, when taking account into the arrangement of wiring lines associated with chips and the size limitation of individual capacitors, it is very difficult to distribute the capacitors so as not to cause any power drop or noise. Further, since the capacitors employed for reducing or minimizing the noise are high frequency and low inductance capacitors, they are expensive, and this causes an inevitable increase in the production cost of the integrated circuits in which they are provided.
On the other hand, with reference to FIG. 2, which is a cross-sectional view of another semiconductor package stack, the package stack (150) is fabricated by stacking a plurality of, for example, four chips (21) and providing the resulting assembly with a cap (95).
To describe in more detail, for the first (lowest) stacked package, a plurality of bonding pads (not shown) formed on the chip (21) are electrically connected to the corresponding leads (22) by bumps (24), and leads (22) are electrically interconnected to each other through conductive layers (95A) formed on the internal opposite side surfaces of the cap (95).
The second through fourth stacked packages are stacked by the same fabrication process as described above.
The conductive layers (95A) of the cap (95) are formed on the opposite internal side surfaces, and commonly electrically interconnect the leads (22) to each other and to the land patterns (82) on the PCB (80). The cap (95) is mounted on the PCB (80) by a known mounting technique.
This type of package stack has a drawback, compared to that shown in FIG. 1A, in that the space between the lowest stacked package and the PCB is too narrow to permit the manufacturer to form and put in place a capacitor for reducing the noise beneath the lowest stacked package. If the formation of capacitor is desired, a separate space should be set aside for its location, causing a set-back in attempting to meet the objective of increasing the mounting density. Accordingly, there has been a need to provide a high speed, low noise semiconductor package stack without at the same time producing a disadvantage of reducing the mounting density. The present invention fulfills this need.